This invention relates to a signal transmission system for transmitting signals through circuit elements generating a dispersion, such as make-and-break contacts.
In recent years, various such apparatuses have been constructed using microprocessors or microcomputers. Usually, the signal transmission between the apparatuses constructed of the microcomputers is performed by a transmission system which employs dedicated elements, for the Serial Transmission Element 8251A from Intel Inc. With these transmission elements, the transmission is based on clock pulses of fixed period, and a problem concerning the delay time of the signal transmission is hardly posed.
However, regarding the transmission among many sorts of apparatuses as in, for example, an overall monitoring system described in the official gazette of Japanese Utility Model Registration Application Laid-open No. 58-127064, the transmission among the apparatuses which are per se constructed of microcomputers or computers employs a method wherein voltages are raised and then transmitted through make-and-break contacts in order to increase the noise bearing capacity.
FIGS. 7 and 8 show a signal transmission system in a prior art.
Referring to the figures, letter T designates a driver unit which generates ON-OFF signals, and letter R a receiver unit which receives the signals transmitted by the driver unit T. Symbol T1 denotes a chip select signal of the transmission port of the driver unit T, and symbol R1 represents a chip select signal of the receiver unit R. Symbol T2 denotes a write signal from a central processing unit (hereinbelow, abbreviated to `CPU`), while symbol R2 denotes a read signal from a CPU. Symbols T3 and R3 indicate data buses for the driver unit T and the receiver unit R, respectiely. An AND element T4 is supplied with the chip select signal T1 and the write signal T2 as inputs, while another AND element R4 is inputted with the chip select signal R1 and the read signal R2. Latch circuits T11-T18 store data of 1 byte delivered to the data bus T3 of the CPU, when the output of the AND element T4 is an enable signal. Sending microrelays T21-T28 convert the output signals of the latch circuits T11-T18 into contact signals, respectively. Receiving microrelays R21-R28 receive the contact signals from the microrelays T21-R28, respectively. Gate circuits R11-R18 supply the data bus R3 with the contact signals of the respective receiving microrelays R21-R28 when the output of the AND element R4 is enabled. Symbol (-) denotes a low negative pole of a D.C. source, and symbol (+L) denotes a positive pole thereof, for which 5 volts is employed by way of example. Symbol (+H) denotes a high positive pole for which 24 volts is employed by way of example. Symbol CBL denotes cables which connect the driver unit T and the receiver unit R.
Next, the operation of the prior-art system will be described.
When the chip of the driver unit T is selected to become a write timing, the enable signal is provided from the AND element T4, and the 8-bit (1-byte) data of the data bus T3 is stored in the latch circuits T11-T18. The sending microrelays T21-T28 are electromagnetic relays operative responsive to the energization of the relay coils which depends on the stored contents of the latch circuits T11-T18. A high voltage level from the latch circuit representing a 1-bit will energize the relay coil to engage the contacts of the relay to provide a high voltage level as an ON signal. On the contrary, a low voltage level from the latch circuit will render the relay coil inoperative and, in turn, the contacts remain separate, providing a low voltage level as an OFF sigal. The ON and OFF signals are then transmitted to the receiver unit R through a transmission medium represented in FIG. 7 as cables CBL. On the receive side, the relay coils of the receiving microrelays R21--R28 are correspondingly energized in response to the ON or OFF signals transmitted from the driver unit T. An ON signal representing a 1-bit will activate the microrelay to produce a voltage level (+L) at its output by engaging its contacts. An OFF signal representing an O-bit, on the other hand, will render the microrelay inoperative and zero voltage is produced at its output. Similarly, as in the driver unit T, the voltage level (+L) denotes a 1-bit while the zero voltage level denotes an O-bit.
When the chip of the receiver unit R is selected to become a write timing, the enable signal is provided from the AND element R4, and the voltage level outputs from the receiving microrelays R21-R28 are received at the latched circuits R11-R18 which in turn output the bit information onto the data bus R3.
However, in the circuit shown in FIG. 7, the operations of the sending microrelays T21-T28 and the receiving microrelays R21-R28 disperse. This will be explained with reference to FIG. 8.
In the figure, b0-b6 indicate bit signals, and the sending microrelays T21-T28 operate in response to the signals of 1 byte from the CPU. b10-b16 similarly indicate bit signals, and the receiving microrelays R21-R27 operate in response thereto respectively. The operating states of the sending microrelay T28 and the receiving microrelay R28 shall be omitted from the description.
It is now assumed that the CPU on the sending side have judged to deliver the signals at a time TA indicated in FIG. 8. When the bit signals are fed on the data bus T3 and the enable signal is further generated by the AND element T4, the latch circuits T11-T17 store the bit signals (since the period of time taken from the judgement of the delivery by the CPU till the storing operations of the latch circuits T11-T17 is very short and the operations disperse little, the time TA may well be deemed a time at which the latch circuits T11-T17 have stored the bit signals). The sending microrelay T21 operates at a time t0 and provides a low level signal (hereinbelow, termed `L signal`), on the basis of which the receiving microrelay R21 provides an L signal at a time t10. The other signals similarly become L signals at times t5.fwdarw. t11-t5.fwdarw.t15, respectively. The bit signal b16 becomes a high level signal (hereinbelow, termed `H signal`) at a time t6, whereupon the receiving microrelay R27 provides an H signal at a time t16.
Here, it is assumed that the receiving microrelay R25 operate fastest with: EQU Operating time interval LT.sub.min =Time t14-Time TA (1)
It is also assumed that the receiving microrelay R26 operate most slowly with: EQU Operating time interval LT.sub.max =Time t15-Time TA (2)
Then, the dispersion of the operating time intervals OFF(t) in which the bit signals b10-b16 turn from the H signals to the L signals becomes: EQU OFF(t)=LT.sub.min -LT.sub.max ( 3)
Likewise, the dispersion of the operating time intervals ON(t) in which the bit signals b10-b16 turn from the L signals to the H signals becomes as follows: EQU ON(t)=HT.sub.min -HT.sub.max ( 4)
where
HT.sub.min : minimum operating time interval, PA1 HT.sub.max : maximum operating time interval. PA1 TD.sub.min : time interval of the smaller one of LT.sub.min and HT.sub.min PA1 TD.sub.max : time interval of the greater one of LT.sub.max and HT.sub.max
Accordingly, the dispersion of the time intervals in which the signals of 1 byte have been transmitted is as follows: EQU TD.sub.min -TD.sub.max ( 5)
where
In order to read a correct signal, therefore, the receiver unit R must perform a reading operation at or after a time TC at which at least the time interval TD.sub.max has lapsed since the time TA.
Assuming that the receiver unit R have read the signals of 1 byte at a time before the lapse of the time interval TD.sub.max, for example, at a time TB as indicated in FIG. 8, the bit signals b12 and b15 do not become the L signals yet, and an erroneous signal is transmitted. This incurs the following drawback in, for example, a system wherein the cage position of an elevator is sent with binary signals of bits 0-6. At the time TA in FIG. 8, the position is a floor 3FH in the hexadecimal system (H indicates the hexadecimal system, and 3F corresponds to the bit signal b.sub.0 -b.sub.6, namely 0111111 or 63 in the decimal system), whereas at the time TB, it becomes a floor 64H (corresponding to 1100100 bit values of bit signal b.sub.10 -b.sub.16 or 100 in the decimal system), so that the cage position signal is not transmitted correctly.
With the prior-art signal transmission system constructed as described above, in case of transmitting a signal through a device, e.g., a made-and-break contact which is lower in the operating speed than a CPU, the CPU has sometimes read the state in which the contact is operating and is not stabilized yet. This has led to the problem that the signal is not received correctly.